A common structure in various electronics packages, such as laminate packages, wired circuit boards, ceramic substrates, and hybrid circuits, is a via. A via is a vertical opening which can be filled with conducting material used to connect circuits on various layers of a substrate or electronics packages to one another. Vias in certain devices may connect to a semiconducting substrate. A via generally starts as an empty cylindrical opening in an electronics package which is formed by drilling. The via is then plated with an electrical conductor such as copper or tin. Plating may be done over the entire panel or device, or may be done with a pattern, dot, or button feature. The plating process results in a via that is an opening with a plated, electrically conductive layer on the inner surface of the opening. Plating may also result in plating all or part of the surface of the device. Plating of the via provides the primary electrical contact at the various layers within the device. The following step is to fill the via with an electrically conductive, thermally conductive or nonconductive paste. The reasons for filling the via after plating include providing a secondary or fail safe electrical connection, or to provide structure integrity, to prevent chemical process entrapment from down-line operations, or to provide thermal conductivity to remove heat from the inner circuit layers of the resulting device. Another reason is that filling the via also controls the breaking of electrical connections formed when the plate or finished electrical device thermally cycles between operating temperatures and non-operating temperatures.
Via filling can occur in the preliminary steps of laminate manufacture, in interim micro-vias, buried vias, blind vias, as well as for pre-gold plate near the end of the end of package/board.
Sequential Build-Up begins with the construction of the “Core Material”, meaning a single or multi-layer copper/resin construction having copper foil on the top and bottom surface. The foil can be of varied thickness noted in terms of ounce weight, ½ oz., ⅜ oz. and the like. The core is normally mechanically drilled to meet design specifications, de-burred, then cleaned and plated with copper. These plated vias require filling with material which will then be covered “capped” with a plated conductive material such as copper.
There are some basic approaches to plating the core panels, such as panel plate (non-featured surface), button plate, pattern plate and full build; the first three usually distinguished by electrolytic processes and the last an electroless process. We will briefly expand upon the first three approaches as examples of how the plating features relate to the via fill process. Panel plate affords the easiest method of processing of via fills. The entire surface of the panel is plated, including the drilled vias. Because there is no patterned topography, the via fill material can be directly applied to the surface by squeegee contact or other means without a patterned stencil or screen. This eliminates the need for extremely accurate registration of a stencil to the patterned vias. For both button plate, and pattern plate, a resist image is applied, plated, stripped, then via fill is applied by registered stencil, sometimes aided by a resist. The reason for the resist: patterned vias have a raised land (annular ring) that can vary from 52+ microns wide (typically), and have a thickness of 16 to 52 microns. This creates a gasket problem for the stencil, especially when one has to register to x, y, theta across an 18″×24″ panel. There are positive and negative aspects for each of these methods. We'll look at the two most basic ones. Panel plating offers ease of via fill application and leveling by means of planarization, but is limiting in its ability to produce the finer features sought for higher circuit density. Pattern plate offers the better line-space definition, but creates intense registration issues with the stenciled via fill process, and exacerbates any overfilling, or resin bleed-out onto surfaces that must remain pristine. In Japan, the tendency is to panel plate, and also to ease registration issues by reducing panel size. This reduces population and profitability per panel as well. Here in the United States, for the most part manufacturers try all three plate-up processes.
The intent is to uniformly plate the drilled via walls at a satisfactory ratio to the core panel's surface. Quite often plating thickness uniformity can be off, causing varied plated wall thickness, “knee” (excessive plate-up at the top and bottom of the plated via walls). There can also be nodules formed by the plating solution within the vias. These issues can also cause problems with via fill uniformity, especially with the squeegee print filling processes, as material flow is non-uniformly restricted in random vias. The size and depth of the drilled/plated vias will depend on the number of layers within the core panel itself. The thicker the panel, and smaller the via diameter, the more difficult the subsequent plating and via filling operation. There are planarization steps that can be used to help gain surface uniformity, but generally it is best to avoid this step by better plating bath control.
In terms of via fill processing, currently used application methods may lead to potential defects that might be caused by preparation of the materials, or the application method itself. The application method and potential defects will now be discussed.
Squeegee blade application consists of using a metal, polymer, or composite blade to force via fill material through the via holes, using a roll-effect pumping action caused by the squeegee being moved forward at a given angle to that of the substrate under process. This roll effect provides a source for air entrapment within the material, which then forces the air into the via. For aspect ratios greater than 4:1, it is often necessary to perform multiple passes. This process provides additional air pockets in the material that are transferred into the via as voids. Using the squeegee process over bare substrate requires strict control of material volume in front of the squeegee, leaving the process subject to excess variability in material transfer into the vias, and varying air bubble entrapment. In addition, large area exposure of the via fill material may introduce contaminants to the paste. This process normally exhibits excessive material waste, the need to add more paste to replenish volume in front of the squeegee, (additional air entrapment), and can lead to divot or material drag-out caused by the trailing edge of the squeegee, leading to poor leveling. Leveling (by sanding) becomes non-uniform.
Squeegee over imaged resist results in slightly reduced waste, since there is less material to planarize. However, this process has the same problems as above, with slightly less divot potential. Furthermore, there is a possibility of co-cure of resist, which can lead to strip problems.
Squeegee over stencil provides slightly improved control over material waste and allows two-way printing, but also requires accurate optics/registration to meet typical theta specification(s) for HDI. A stencil increases the potential for air entrapment. Gasketing over via annular rings becomes an issue since loss of fluid pressure over a via may lead to incomplete filling. A single pass fill is required, or an air pocket equal to the stencil aperture volume is forced into the via.
Squeegee over emulsed/imaged screen improves gasketing, but introduces pattern stretch. The screen mesh used greatly increases air entrapment. The screen emulsion compatibility with fill material may also be an issue. Registration repeatability becomes more difficult and a single pass is required to avoid additional air pockets.
As discussed above, the current manufacturing processes associated with filling vias with paste has several problems. In the past it has been difficult to reliably place paste in a via without forming an air pocket or void. The via must be completely filled with paste so that there are no air pockets. If there are voids or air pockets in the paste, these air pockets generally remain in the completed product. A via with a void has several adverse effects. If the paste is placed to provide thermal conductivity, the air of the void is an insulator. If the paste is placed to provide electrical conductivity, if an open should occur at the void there will be no secondary or fail safe electrical connection that can be formed. Furthermore, if the via is filled to provide structural integrity, a void in the via provides for less structural integrity.
Among the effects are that air acts as an insulator, not being as conductive as the paste or plating material. As a result, a via with a void is not as electrically conductive as a via completely filled with conductive materials. The void could also result in an open contact. In addition, the void is within the via and cannot be seen, may produce a micro pin-hole which can hold process fluid contaminants. In addition, air acts as an insulator with thermally conductive fill materials, and the void reduces the thermal conductivity of the filled via. In some instances, a via that contains an air pocket or void may result in the electronics package failing to meet manufacturing specifications. The electronics package may be rejected. Rework may be possible, but would be time consuming. In other instances, the electronics package may have to be scrapped which would reduce the yield percentage associated with the manufacturing process.
The problems set forth above are magnified when a smaller diameter, higher aspect ratio via is required. Smaller diameter, higher aspect ratio vias are becoming more popular as the miniaturization of electronics packages continues to form more densely populated products. Vias to be filled may range from 2–25 thousandth of an inch in diameter and currently have had a depth to diameter ratio from 1:1 to 10:1. The industry struggles to fill vias with aspect ratios greater than 6:1
Thus, there is a drive to establish a method and apparatus to reliably fill vias since filled vias provide numerous advantages in the developing HDI (High Density Interconnect) and SBU (Sequential Build-Up) technologies.
In addition, the exponential growth of organic laminate package and board production has pressed manufacturers to ever increasing interconnect densities, while shrinking size and cost per unit. A good example of this would be the sheer volume growth of throwaway cell phones. Smaller size, lower cost, and performance are critical for competitive marketing on a global scale. At the same time, the demand for filling of via holes has been rising ever since surface mount technology (SMT) became a PCB industry standard. Inner layers are often filled by resin flow during lamination, and as with Plastic Land Grid Arrays (PLGA's), re-flowed solder materials had been used as a structural reinforcement for plated thru-holes, with the added property of high conductivity for potentially bridging any opens caused by wall cracking or other defects.
The designers of High Density Interconnect (HDI) boards and HDI or, Sequential Build Up (SBU) packages are now relying on the ability to utilize various via fill materials to enhance reliability and performance of their designs. The demand, for the most part, had been for non-conductive via fill materials. The via fill applications were basically intended to have two functions; to prevent carry-over contamination from post-fill processing, and to provide some structural support. Although not a standard industry practice, this application demonstrates an area in which improvements of a via fill material, specifically it's conductivity, will greatly simplify package and board processing. Thus, there is great interest in advantages of thermal and electrically conductive material use for improved reliability. Combined with feature size reduction, the filling of features such as through-holes, blind vias, and via in pad with conductive/non-conductive materials plays an enabling role towards this growth.
In conclusion, there is a need for a method and apparatus for placing paste into via openings in electronic packages so that there are no air pockets formed in the paste. There is also a need for a process and apparatus which can be used to form a plugged via which has a reliable electrical contact and which has favorable thermal characteristics. There is also a need for a process which can improve yield for forming plugged vias in electronic packages. There is still a further need for a manufacturing process which is controllable and which has a higher throughput during manufacturing, such as in a relatively high speed, single pass operation. There is also a need for a process that can be adapted for use with stencil printing machines currently used in the manufacturing process. There is also a need for a device which will lessen the possibility that contaminates will be introduced into the via fill paste. Furthermore, there is a need for a device that can be used to place paste in vias having high aspect ratios and small diameters. There is further need for an apparatus which has added control for filling the vias.